(1) Field of the Invention
The present invention relates to a bipolar-MIS logic circuit in which bipolar transistors and MIS transistors are combined, and more particularly to a bipolar complementary MIS static logic circuit (hereinafter referred to as "BiCMIS logic circuit"), a dynamic logic circuit and a semiconductor integrated circuit, which are suited to an ultra high-speed operation where a power supply voltage is low.
(2) Description of the Related Art
A logic circuit which utilizes a combination of bipolar transistors and CMIS transistors and which is the so-called a BiCMIS logic circuit is disclosed, for example, in the U.S. Pat. Nos. 4,558,234; 4,616,146; 4,638,186; and 4,769,561.
FIG. 1 shows a BiCMIS logic circuit disclosed in the U.S. Pat. No. 4,769,561. The circuit is formed by two output bipolar transistors 11, 12 and four MIS transistors 13, 14, 15 and 16. This circuit is advantageous in view of low input capacitance, high output driving capability, high speed operation and low power consumption, and is widely used for memories in LSIs which require high performance. However, a problem in this circuit is that, although it can enjoy the above advantages at a power supply voltage in the neighborhood of 5 V, the high speed capability is suddenly lost at the power supply voltage in the neighborhood of 3 V. The deterioration of the high speed capability caused by the lowering of the power supply voltage is, as shown in FIG. 2, due especially to a remarkable increase in the falling delay of an output signal S.sub.OUT with respect to an input signal S.sub.IN. FIG. 3 shows the power supply voltage dependency of such falling delay, in which a solid line represents the power supply voltage dependency of the CMIS logic circuit and a dotted line represents that of the BiCMIS logic circuit (inverter). As apparent from these graphs, in the conventional BiCMIS logic circuit, the advantage as a high speed logic is lost at supply voltages lower than 4.0 V.
The deterioration of the high speed capability, which is unique to the BiCMIS circuit, is mainly due to the fact that the base current of a bipolar junction transistor (hereinafter referred to as "BJT") suddenly decreases for such reason that a drain-source voltage V.sub.ds of the N-channel MIS transistor (hereinafter referred to as "NMIS") 15 is lowered due to a base-emitter voltage V.sub.be.
FIG. 4 shows a circuit diagram disclosed in the U.S. Pat. No. 4,558,234. This circuit is formed by one bipolar transistor 21 and three MIS transistors 22, 23 and 24. This circuit utilizes the BJT 21 for an output pulling-up and the NMIS 22 for an output pulling-down. Since this circuit does not use a BJT as a pull-down transistor, there is no sudden speed deterioration even at a power supply voltage in the neighborhood of 3 V. However, since the NMIS 22 is employed for a pull-down transistor, the falling time of an output is greatly delayed when a heavy load capacitance is driven. If an attempt is made to improve the driving capability by increasing the conductance of the NMIS, the gate capacitance becomes large resulting in a deterioration of operation speed of a circuit of a previous stage. There is also a disadvantage in that a self-delay increases due to the transistor's own drain junction capacitance.
A trend today is that, for the power supply voltages in LSIs, the lowering of such voltages is inevitable in order to cope with the decrease in element resistance due to furtherance of miniaturization of semiconductor devices and to solve the problem brought about by a need for speeding up of systems or by an increase in power consumption due to higher integration in semiconductor devices. Thus, there is a strong desire for realization of a BiCMIS logic circuit which has the same high performance as the conventional circuit even when the power supply voltage is low.
With the conventional BiCMOS logic circuit explained above, a switching speed suddenly and largely deteriorates when the power supply voltage is lowered near to 3 V and this renders the circuit unsuited to a high speed logic circuit of the next generation.